1. Field of the Invention
The present invention relates to a reliability testing method for semiconductor ICs, and more particularly, to a method for reliability testing that not only reduces the cost of burn-in testing, but also improves the reliability of the IC products.
2. Background of the Invention
An index of the reliability of a wafer is the failure rate, which is termed xe2x80x9cfitxe2x80x9d (failure unit), and is the total number of device failures in 109 device-hours. The reliability of a wafer indicates the survival rate (as opposed to the failure rate); the higher the survival rate, i.e. the lower the failure rate, the better the reliability of the product.
Please refer to FIG. 1. FIG. 1 is a graph of failure rate vs. lifetime for a semiconductor product according to the prior art. As shown, a semiconductor product has a higher failure rate at the beginning of its life time, but as time goes by, its failure rate decreases in stage A, which is also called the xe2x80x9cinfant mortality stagexe2x80x9d. As the product passes a certain point in its lifetime, the failure rate reaches the lowest point in stage B, which is also called the xe2x80x9cuseful life stagexe2x80x9d. After passing the useful life stage, the product""s failure rate increases rapidly in stage C, which is also known as the xe2x80x9cwear out stage.xe2x80x9d The infant mortality stage, useful life stage and wear out stage that a semiconductor product goes through form a curve shaped like a bathtub. A testing engineer decides if a product is to be sold or discarded by measuring its failure rates in the three stages and checking if it is lower than a required failure rate.
Please refer to FIG. 2. FIG. 2 is a flow chart of a reliability test for wafers according to the prior art. As shown here, a semiconductor wafer is manufactured in step 10, the wafer comprising a plurality of dies. Next, in step 12, a circuit probe test is performed on the wafer, which is also called a wafer probe test. According to this testing result, the dies are sorted into functional dies and non-functional dies. The non-functional dies do not participate in the rest of the testing processes. The functional dies singled out in step 12, however, go through a first a saw and assembly process (step 14), and then a package testing process (step 16). After the package testing process (step 16), a few dies that have broken or failed in the packaging process are discarded, and the majority that have passed the package testing process are sent to a burn-in test, which removes those that fail in infancy (step 18). Finally, a final test is performed on those that have passed the burn-in test to evaluate the quality of the product.
According to the prior art, after a wafer goes through a circuit probe test, all the functional dies go on to the saw and assembly process and the burn-in test. However, the time period of the burn-in test is between 24 and 48 hours, and may sometimes even exceed 48 hours. This wastes a great deal of time, incurring high costs and resulting in uncontrollable failure rates, and may even delay the product release deadline.
It is therefore the primary objective of this invention to provide a selective reliability testing method to reduce production costs and to increase product reliability.
The present invention provides a reliability testing method for wafers. In this method, a semiconductor wafer is first provided, and the wafer comprises at least a first die and a second die, which are grouped into different regions according to a wafer map. A saw and assembly process is executed, packaging the first dies and the second dies into first and second packaged units, followed by a burn-in test. The burn-in test is performed on the first packaged unit for a first testing period to eliminate the dies that have failed in infancy, and is performed on the second packaged unit for a second testing period to eliminate those dies that have fail in infancy. The first testing period is shorter than the second testing period.
These and other objectives of the present invention will no doubt become obvious to those of ordinary skill in the art after having read the following detailed description of the preferred embodiment that is illustrated in the various figures and drawings.